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    • 专利摘要:
    A semiconductor device (100) having at least: - two semiconductor nanowires (104) superimposed one above the other, spaced from one another and intended to form channel regions of the semiconductor device, - a dielectric structure (106, 108) completely filling a space extending between the two semiconductor nanowires and which is in contact with the two semiconductor nanowires, - a gate dielectric (110 ) and a gate (112) covering at least a first of the two semiconductor nanowires, lateral flanks of the two semiconductor nanowires and side flanks of the dielectric structure, and wherein the dielectric structure comprises at least a portion dielectric material (108) of relative permittivity greater than 3.9.
    公开号:FR3016237A1
    申请号:FR1450079
    申请日:2014-01-07
    公开日:2015-07-10
    发明作者:Sylvain Barraud；Pierrette Rivallin；Pascal Scheiblin
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] TECHNICAL FIELD AND PRIOR ART The invention relates to a semiconductor device comprising a plurality of superimposed semiconductor nanowires, spaced from one another and which are partially surrounded by a grid. The invention is advantageously applicable to the production of FET (Field Effect Transistor) type devices, in particular for logic applications with high performance and low consumption of microelectronics. The invention is also applicable to the production of superimposed nanowire MOSFET transistors, for example for the production of integrated circuits having improved electrical performances compared to the circuits of the prior art.
    [0002] The semiconductor nanowires are nanostructures from which it is possible to produce FinFET transistors ("Finshaped Field Effect Transistor" or 3D transistors). In such a FinFET transistor, instead of having an active area corresponding to a planar structure as in a conventional MOSFET type transistor, a "fin", or nanowire, of semiconductor is made in relief on the substrate to form the transistor channel. The advantage of this addition is to increase, without affecting the density with which the transistors are made on the substrate, the contact surface between the gate and the channel at an upper face and side flanks of the channel ( hence the name "Tri-gate transistor" also given for this type of transistor). This increase of the contact area between the gate and the channel makes it possible to reduce the leakage currents when the transistor is in the off state (OFF state). Such a FinFET structure thus makes it possible to produce transistors comprising gate lengths that are smaller than those of planar architecture MOSFET transistors without degrading the electrical performance of the transistors. A FinFET transistor can be manufactured on a bulk or SOI type substrate. The threshold voltage obtained with such FinFET transistors is adjusted by the metal of the gate (fixed by its output work). The modulation of the threshold voltage made possible by an adjustment of the geometric dimensions of the nanowire (width and height) remains however critical and may be incompatible with the constraints related to a good electrostatic control of the transistor, that is to say have a transistor having a low DIBL ("Drain-Induced Barrier Lowering") and a low slope below the threshold S ("Subthreshold Slope"). The conduction current obtained is directly related to the circumference of the defined nanowire, in the case of a nanowire of rectangular section, by the value 2 (H + W), with H corresponding to the height of the nanowire and W corresponding to the width nanowire. With this type of transistor, it is possible to increase the density of nanowires, or fins, on the substrate, and therefore the density of the transistors, to create more efficient devices. The technique for increasing the density of nanowires is called "spacer patterning" or "double patterning" (because it reduces the pitch, or "pitch" of nanowires by two) and consists in producing the nanowires via the following steps a first lithography and an etching are carried out in order to produce patterns, drawn by a first mask, in a resin film, a deposit of a material called "spacer" such as oxide or silicon nitride is performed on the patterns formed in the previous step, - a third step is to engrave the spacer and to remove the resin so that the remaining spacer material defines new patterns on each side of each pattern defined in the first step. The studs thus formed are spacer studs whose pitch is twice as small as that of the studs formed during the first lithography. A fourth step of the method consists in transferring all the patterns by etching into the silicon layer. formed in the hard mask "spacer", thus forming the silicon nanowires, - a second lithography is often necessary to cut the nanowires at their ends, - finally, the spacers are removed and the grid stack is deposited and etched. Such a method is for example described in US 6,709,982 B1 and WO 2008/059440 A2.
    [0003] However, even with such a method, the circumference of the nanowires generally remains large and therefore the electrostatic control is not optimal. There are also GAA-FET type transistors, or GateAll-Around FETs, in which the gate encases, or completely surrounds, the silicon nanowire or nanowires. Compared to the FinFET transistors, the semiconductor nanowires having a fully encapsulating gate of the GAA-FET transistors make it possible to obtain an excellent electrostatic control of the transistors. This significantly reduces the leakage current when the transistor is in the OFF (blocked) state. These GAA type devices are thus envisaged for the most advanced technological nodes for which the gate length is less than 20 nm. However, a disadvantage of this type of transistor is its difficulty of manufacture. Indeed, after the deposition of the grid all around the semiconductor nanowire or nanowires, it is necessary to etch the gate stack which can be composed of an insulating layer (gate dielectric), a gate metal and polycrystalline silicon. However, after the etching of the gate stack, there is still gate metal to be removed, especially under the nanowires in the source-drain extension zones. This removal is difficult to achieve but essential to avoid turning the transistor short circuit. In order to avoid this problem, the grids are often oversized to partially cover the source and drain zones and it is then difficult to reach the target dimensions for the gate lengths of this type of transistor, for example less than 15 nm. .
    [0004] SUMMARY OF THE INVENTION An object of the present invention is to propose a semiconductor device that does not have the drawbacks associated with the production of GAA-FET devices while retaining the advantages provided by the structures of the GAA-type devices. FET compared to other types of FET device. For this, the present invention proposes a semiconductor device comprising at least: two semiconductor nanowires superimposed one above the other, spaced from one another and intended to form channel regions of the semiconductor device, - a dielectric structure completely filling a space extending between the two semiconductor nanowires and which is in contact with the two semiconductor nanowires, - a gate dielectric and a gate covering at least one first of the two semiconductor nanowires, side flanks of the two semiconductor nanowires and side flanks of the dielectric structure, and wherein the dielectric structure comprises at least a portion of dielectric material of relative permittivity greater than 3.9 . With respect to a device of GAA-FET type which comprises a gate dielectric and a gate completely surrounding the nanowire or nanowires of the device and which therefore requires the implementation, during its production, of an etching of a part of the device. electrically conductive material of the gate located under the parts of the nanowire or not forming the channel, especially at the source and drain extension zones, the semiconductor device according to the invention comprises a dielectric structure interposed between the nanowires semiconductor which avoids the implementation of such an etching because the grid surrounds only a portion of the nanowires and is not located under the nanowires. In addition, the semiconductor device according to the invention does not require an oversizing of the grids. Thus, the gate dielectric and the gate of the semiconductor device according to the invention may not cover, even partially, the source and drain areas of the semiconductor device.
    [0005] The semiconductor device according to the invention makes it possible to form a transistor of the FET type retaining a structure close to that of a FinFET-type transistor, that is to say with a channel region, here formed by at least two superimposed nanowires, and a grid arranged on two or three sides of the nanowires, facilitating the etching of the gate during its realization while increasing the drain current and reducing the leakage current of the device via better electrostatic control. The semiconductor device according to the invention makes it possible to maintain the simplicity of manufacturing a FinFET transistor with the implementation of standard gate etching while retaining the advantages (in terms of charge transport properties) of the structures. surrounding grids of GAA-FET devices. Since the portion of dielectric material has a relative permittivity, or dielectric constant, greater than that of SiO 2, that is to say greater than 3.9, the penetration of the electric field lines (this field being induced by the gate located on the flanks of the nanowires during operation of the semiconductor device) in the portion of dielectric material, and therefore under the semiconductor nanowires, is favored. This configuration makes it possible to obtain an electrostatic control close to or identical to that of Gate-All-Around (GAA) devices. The penetration of the electric field lines under the semiconductor nanowires also makes it possible to increase the conduction surface (compared to a standard FinFET device) and therefore the electrical performance of the semiconductor device. The term "dielectric structure" here designates a structure formed of one or more dielectric materials and not comprising an electrically conductive or semiconductor material such as a metal or polycrystalline silicon. The dielectric structure, and in particular the portion of dielectric material, can extend between the nanowires at least at the level of the channel region formed by the nanowires, and for example also at the level of the source and drain extension zones ( LDD "Light-Doped Drain" and LDS "Light-Doped Source" regions). The semiconductor device according to the invention can form a field effect transistor whose gate length is less than or equal to 20 nm, or 15 nm, or even 10 nm.
    [0006] The semiconductor device according to the invention can advantageously be used for the production of integrated circuits serving for high performance and low power microelectronics logic applications such as smartphones, tablets, laptops, etc. The portion of dielectric material may comprise at least one dielectric material of relative permittivity greater than or equal to 20. Thus, the penetration of the electric field lines into the dielectric structure is improved because the greater the dielectric constant, or relative permittivity, of this dielectric material is high, the better is the electrostatic coupling. The semiconductor nanowires may be parallel to one another, that is to say extend in the same direction. In this case, each semiconductor nanowire may comprise, in a plane perpendicular to a direction in which the semiconductor nanowires extend, a section of rectangular shape. The direction in which the nanowires extend corresponds to the orientation of the larger dimension of the nanowires. In this configuration, the gate dielectric and the gate may cover an upper face of the first of the two semiconductor nanowires, as well as the lateral faces of the two semiconductor nanowires and the lateral faces of the dielectric structure. In addition, the portion of dielectric material and the dielectric structure may each comprise, in the plane perpendicular to the direction in which the semiconductor nanowires extend, a section of rectangular shape. Alternatively, it is possible that the section of the semiconductor nanowires, in the plane perpendicular to the direction in which the semiconductor nanowires extend, is circular. In addition, the portion of dielectric material and the dielectric structure may each comprise, in the plane perpendicular to the direction in which the semiconductor nanowires extend, a section of circular shape. Each semiconductor nanowire may be surrounded by a dielectric interface layer, the dielectric structure may further include portions of the dielectric interface layers disposed between the semiconductor nanowires and in contact with the dielectric material portion. . In the absence of such layers of dielectric interfaces, the portion of dielectric material can be directly in contact with the semiconductor nanowires. In the dielectric structure, the thickness of the portion of dielectric material may be greater than or equal to about ten times the thickness of a dielectric interface layer. The semiconductor device may further comprise, when the semiconductor device has more than two semiconductor nanowires superimposed on one another, several dielectric structures such that two of the adjacent semiconductor nanowires may be spaced apart. from one another by one of the dielectric structures extending between said two adjacent semiconductor nanowires and which is in contact with said two adjacent semiconductor nanowires, and the gate dielectric and the gate may furthermore covering lateral flanks of each of the semiconductor nanowires and the lateral flanks of each of the dielectric structures. The semiconductor device may further comprise source and drain regions between which the semiconductor nanowires extend, the dielectric structure being able to come into contact with the source and drain regions and / or juxtaposed with the regions of the semiconductor source and drain. The invention also relates to a method for producing a semiconductor device, comprising at least the steps of: - producing at least two semiconductor nanowires superimposed one above the other, spaced apart from one another and intended to form channel regions of the semiconductor device, - providing at least one dielectric structure completely filling a space extending between the two semiconductor nanowires and which is in contact with the two semiconductor nanowires, - realization of a gate dielectric and a gate covering at least a first of the two semiconductor nanowires, lateral flanks of the two semiconductor nanowires and lateral flanks of the dielectric structure, and wherein the dielectric structure comprises at least a portion of dielectric material of relative permittivity greater than 3.9. The production of the two semiconductor nanowires may comprise at least the implementation of the steps of: etching a stack of at least two semiconductor layers between which is disposed at least one sacrificial layer, such as remaining portions of the two semiconductor layers correspond to the semiconductor nanowires, a remaining portion of the sacrificial layer being disposed between the semiconductor nanowires, - deleting the remaining portion of the sacrificial layer disposed between the semiconductor nanowires -conductor, forming the space extending between the two semiconductor nanowires. The two semiconductor layers may comprise silicon, and the sacrificial layer may comprise SiGe. The step of producing the dielectric structure may comprise at least one deposition of the portion of dielectric material between the semiconductor nanowires. The step of producing the dielectric structure may further comprise, between the step of producing the two semiconductor nanowires and the step of depositing the portion of dielectric material, a step of producing a dielectric layer. dielectric interface around each semiconductor nanowire, the portion of dielectric material being subsequently deposited against portions of the dielectric interface layers disposed between the semiconductor nanowires. The method may further comprise the production of source and drain regions between which the semiconductor nanowires extend, the dielectric structure being able to be made in contact with the source and drain regions and / or juxtaposed with the regions of the semiconductor nanowires. source and drain.
    [0007] BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be better understood on reading the description of exemplary embodiments given purely by way of indication and in no way limiting, with reference to the appended drawings in which: FIG. 1 represents a front sectional view of several semiconductor devices, objects of the present invention, according to a particular embodiment, - Figures 2 to 6B show the steps of a method of producing several semiconductor devices, objects of the present invention, according to a mode In particular, FIG. 7 represents the values of the ratio of the electron concentrations at the upper and lower faces of a semiconductor nanowire of a semiconductor device, object of the present invention, as a function of the relative permittivity of a portion of dielectric material of the semiconductor device and the width of the semiconductor nanowire ucteur.
    [0008] Identical, similar or equivalent parts of the different figures described below bear the same numerical references so as to facilitate the passage from one figure to another. The different parts shown in the figures are not necessarily in a uniform scale, to make the figures more readable. The different possibilities (variants and embodiments) must be understood as not being exclusive of each other and can be combined with one another. DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS Referring firstly to FIG. 1, which represents a front sectional view of a plurality of semiconductor devices 100 according to a particular embodiment. In this particular embodiment, each of the semiconductor devices 100 corresponds to a transistor of FET type with superimposed nanowires.
    [0009] The semiconductor devices 100 are made on a dielectric layer 102 for example based on semiconductor oxide such as SiO 2. This dielectric layer 102 may itself be arranged on a bulk substrate (not shown) of a semi-conductor, for example based on silicon, or may correspond to a buried dielectric layer of a semiconductor-on-insulator substrate. forming for example a BOX (buried oxide) of a SOI substrate (silicon on insulator). In the particular embodiment described here, the dielectric layer 102 is a thick dielectric layer, its thickness (dimension along the Z axis shown in Figure 1) being for example equal to about 145 nm. Each of the semiconductor devices 100 comprises several semiconductor nanowires 104 (at least two), for example based on silicon and / or germanium and / or any III-V semiconductor, superimposed on one another others and spaced from each other by dielectric structures formed of one or more dielectric materials. In the exemplary embodiment shown in FIG. 1, each of the semiconductor devices 100 comprises three semiconductor nanowires 104. As a variant, each of the semiconductor devices 100 can comprise two nanowires, or four nanowires, or more nanowires. four nanowires, superimposed one above the other. The parts of the semiconductor nanowires 104 shown in FIG. 1 form channels of the semiconductor devices 100 which extend between source and drain regions (not visible in FIG. 1) of the semiconductor devices 100, parallel to the Y axis.
    [0010] In the embodiment described here, the sections of the semiconductor nanowires 104 in the plane (X, Z), that is to say in a plane perpendicular to the direction (parallel to the Y axis) according to which the semiconductor nanowires 104 extend, are of square shape. However, these sections could be of different shape, for example rectangular or circular.
    [0011] Each of the semiconductor nanowires 104 has a height HNW, or thickness, corresponding to the dimension along the Z axis shown in FIG. 1, for example equal to approximately 10 nm or 12 nm, or more generally between approximately 5 nm. and 30 nm. Each of the semiconductor nanowires 104 has a width WNW, corresponding to the dimension along the X axis shown in FIG. 1, for example equal to approximately 10 nm or 12 nm, or more generally between approximately 5 nm and 30 nm. . Each of the semiconductor nanowires 104 may also have a length LNW, corresponding to the dimension along the Y axis shown in FIG. 1, for example between about 5 nm and several hundreds of nanometers. The centers of two neighboring semiconductor nanowires 104 lying in the same plane parallel to the surface of the dielectric layer 102 on which the semiconductor devices 100 (parallel to the plane (X, Y)) are formed and which belong to two neighboring devices 100 are spaced apart by a distance PNW, for example equal to approximately 30 nm (the space separating these two semiconductor nanowires 104 being, for example, equal to approximately 20 nm), or more generally between approximately 15 nm and several hundred nanometers. In this particular embodiment, each of the semiconductor nanowires 104 is surrounded by a dielectric interface layer 106, for example based on SiO 2 (relative permittivity equal to 3.9) and having a thickness equal to about 0.8 nm or between about 0.7 nm and 10 nm. These layers of dielectric interfaces are here in direct contact with the semiconductor nanowires 104. These dielectric interface layers 106 make it possible to reduce the interface defects and thus to obtain better transport properties in the semiconductor structure. These interface layers 106 are for example made as thin as possible in order to maintain excellent electrostatic coupling. In each of the semiconductor devices 100, portions of the dielectric material 108 are disposed between the semiconductor nanowires 104, each of the dielectric material portions 108 being in contact with the dielectric interface layers 106 surrounding the semiconductor nanowires. conductor 104 between which is the portion of dielectric material 108. Thus, in each of the semiconductor devices 100, the space between two nanowires 104 superimposed one above the other is completely filled by a dielectric structure formed portions of the dielectric interface layers 106 surrounding each of these two semiconductor nanowires 104 and located between these two semiconductor nanowires 104 as well as one of the portions of dielectric material 108 in contact with these portions of the semiconductor nanowires 104 and dielectric interface layers 106. In the embodiment described here, the sections of the dielectric material portions 108 are s the plane (X, Z), that is to say in a plane perpendicular to the direction (parallel to the Y axis) according to which the semiconductor nanowires 104 extend, are of square or rectangular shape . The shape of these sections may, however, be different because it depends in particular on those of the semiconductor nanowires 104 (and therefore also those of the dielectric interface layers 106) because the portions of the dielectric material 108 are made by filling completely. the space between the semiconductor nanowires 104 surrounded by the dielectric interface layers 106. Each of the dielectric portions 108 has a height HHK, or thickness, corresponding to the dimension along the Z axis shown in FIG. 1 for example equal to about 12 nm, or more generally between about 5 nm and several tens of nanometers. Each of the portions of dielectric material 108 here has a width, corresponding to the dimension along the X axis shown in FIG. 1, equal to the sum of the width WNW of one of the semiconductor nanowires 104 and twice the the thickness of one of the dielectric interface layers 106, for example equal to about 11.6 nm, or between about (WNW + 2 (thickness of one of the layers 106)) and (WNW 6 nm). As a variant, one or more or each of the portions of dielectric material 108 may have a width smaller than WNW of a few nanometers, for example by producing a slight "recess" or recess of the lateral flanks of the portions 108, which makes it possible to further improve the electrostatic control of the device.
    [0012] Each of the portions of dielectric material 108 may also have a length, corresponding to the dimension along the Y axis shown in FIG. 1, for example equal to LG ± 10 nm 'with LG corresponding to the gate length of the device, this which makes it possible to keep this high permittivity material under the gate of the device, that is to say of the FET transistor produced. The centers of two adjacent portions of dielectric material 108 lying in the same plane parallel to the surface of the dielectric layer 102 on which the semiconductor devices 100 (parallel to the plane (X, Y)) are formed and which belong to two 100 neighboring semiconductor devices are spaced from the PNW distance. The portions of dielectric material 108 are based on a dielectric material with a high relative permittivity, that is to say with a relative permittivity greater than that of SiO 2 which is equal to 3.9, for example TiO 2 (ER = 80 ) and / or HfO2 (ER = 25) and / or ZrO2 (ER = 25) and / or Ta205 (ER = 22) and / or Al203 (ER = 9) and / or Si3N4 (ER = 7) and / or HfSiON (ER = 20) and / or SrTiO3 (ER = 2000) and / or 1'203 (ER = 15). Advantageously, the dielectric material of the portions 108 is chosen from those whose relative permittivity is between about 20 and 80. Thus, under similar environmental conditions, the relative permittivity of the dielectric material of the portions 108 is greater than that of the SiO 2. Other piezoelectric type materials whose dielectric permittivity is high (for example PZT whose permittivity is between 200 and 4000, or BaTiO3 whose permittivity is equal to about 1700) can be used. The semiconductor nanowires 104, surrounded by the dielectric interface layers 106, and the dielectric portions 108 form, for each of the semiconductor devices 100, an alternating stack of semiconductor nanowires and dielectric structures. These stacks are covered by gate dielectrics 110. In each of the devices 100, the gate dielectric 110 covers the lateral flanks of the stack, that is to say the lateral flanks of the portions of dielectric material 108 as well as the parts of the dielectric interface layers 106 covering the lateral flanks of the semiconductor nanowires 104. Each gate dielectric 110 also covers a first of the semiconductor nanowires 104 of each stack, that is to say one face upper part of the stack here formed by the portion of the dielectric interface layer 106 covering the upper face of the first semiconductor nanowire 104 (i.e., the semiconductor nanowire 104 lying above of the other semiconductor nanowires 104 of the semiconductor device 100). The gate dielectrics 110 correspond to layers of dielectric material with a high relative permittivity (greater than 3.9), for example based on HfO 2 and having a thickness of approximately 2.5 nm. Each of the gate dielectrics 110 is covered by an electrically conductive grid 112, for example metallic, corresponding here to a TiN layer of thickness, for example equal to approximately 5 nm.
    [0013] Each of the semiconductor devices 100 thus forms a transistor FET whose channel is formed by superimposed semiconductor nanowires 104 and whose gate 112 covers two or three sides of each of the semiconductor nanowires 104, the other sides of the semiconductor nanowires 104. semiconductor nanowires 104 which are not covered by the gate 112 and the gate dielectric 110 being in contact with the dielectric structures which comprise the portions of dielectric material 108 with a high dielectric permittivity. This high dielectric permittivity of the portions of dielectric material 108 facilitates the penetration of the electric field lines (which is induced, during the operation of the device 100, by the gate 112 located on the sides of the semiconductor nanowires 104) in the portions of dielectric material 108, and thus between the semiconductor nanowires 104 forming the channels, which makes it possible to increase the drain current and to reduce the leakage current by better electrostatic control of the transistors formed by the semiconductor devices 100 which is close or identical to that of GAA-FET transistors. With respect to a FinFET type transistor, the penetration of the electric field lines between the semiconductor nanowires 104 also makes it possible to increase the conduction surface, and therefore the performance of the transistor formed by the semiconductor device 100. structure also provides other advantages related to the method of producing the semiconductor device 100 which are described later. In addition, although not visible in FIG. 1, the semiconductor devices 100 also comprise source and drain regions between which the semiconductor nanowires 104 extend. Source and drain extension zones formed by the ends of the semiconductor nanowires 104 are also in contact with the portions of the dielectric material 108 and are therefore not completely surrounded by the gate 112 and the gate dielectric 110. In addition, the portions of the dielectric material 108 are juxtaposed with the source and drain regions. Alternatively, it is also possible that the portions of dielectric material 108 are arranged just below the gate and that they do not extend into the source and drain regions. According to a variant of the particular embodiment described above, it is possible that at least a part of each of the semiconductor nanowires 104 or of some of the semiconductor nanowires 104 is not surrounded by the dielectric interface layers. In such a variant, one of the portions of dielectric material 108 is directly in contact with the two semiconductor nanowires 104 between which this portion of dielectric material 108 is disposed. Moreover, in this configuration, the gate dielectric 110 is also in direct contact with the lateral flanks of the semiconductor nanowires 104. According to this variant, the width of at least one or each of the portions of the dielectric material 108 may equal to the width WNW of each of the semiconductor nanowires 104 between which is the portion of dielectric material 108.
    [0014] According to a second variant, it is possible for the width (dimension along the X axis) of at least one or each of the portions of dielectric material 108 to be smaller than that of each of the semiconductor nanowires 104 between which the portion of dielectric material 108 or, when the semiconductor nanowires 104 are surrounded by the dielectric interface layers 106, less than the sum of the width of one of the semiconductor nanowires 104 and twice the width of thickness of one of the dielectric interface layers 106. According to this configuration, the lateral sides of the stacks of the semiconductor nanowires 104, the dielectric interface layers 106 and the portions of the dielectric material 108 comprise portions of the troughs. dielectric material 108. This difference in width is for example between 0 and 6 nm and allows to promote a little more electrostatic control in such a device sem i-conductor 100. This difference in width is for example equal to about 3 nm. According to this second variant, the width WNW of each semiconductor nanowire 104 is for example between about 5 nm and 10 nm, and the height HHK of each portion of dielectric material 108 is for example between about 10 nm and 20 nm . The height HNW of each semiconductor nanowire 104 is for example equal to 12 nm. In this configuration, the gate dielectric 110 and gate 112 may be in only a portion of the total space between two nanowires 104 superimposed one above the other, i.e. at the level of the depressions formed by the portions of dielectric material 108 at the sidewalls of the stacks of the semiconductor nanowires 104 and the dielectric structures.
    [0015] That the widths of the portions of the dielectric material 108 are equal to or smaller than those of the semiconductor nanowires 104, the semiconductor nanowires 104 and the portions of the dielectric material 108 of a semiconductor device 100 can be made such that the electron concentrations at the upper and lower faces of each nanowire 104 (corresponding to the faces of the nanowires 104 which are parallel to the surface of the layer 102 on which the semiconductor devices 100 are made) are equal to or close to one of the other, for example such that their ratio R is at least about 0.8. This ratio R, which depends on the parameters of the nanowires 104 and the dielectric portions 108 of the semiconductor device 100, can be evaluated according to the following equation: R = 0.53933 + 0.030552.ER + 147.59613.B - 160,12808.WNw + 16.6.HHR - 1.3622.ER.B + 0.6426.ER.WNw + 0.15974.ER4HHR - 10868.B.WNw - 1229.455.B.HHK + 1748, 2777.WNw.HHK - 5,6531.10-4.ER2 + 6744,84.WNw2 - 807,16.HHK2 + 167,3184.ER.B.WNw + 0,012275.ER2.WNw with ER: relative permittivity of the dielectric material portions 108, B: difference between the width of one of the nanowires 104 and the width of one of the portions of dielectric material 108.
    [0016] The curves shown in FIG. 7 correspond to the values of the ratio R as a function of the value of ER (in the abscissa), which is here between 3.9 and 80 E0, and the value of WNw (in the ordinate), which is here between 0.005 μm and 0.01 μm, choosing B = 3 nm and HHK = 20 nm. The curve bearing the reference 50 corresponds to the pairs of values (ER; WNw) making it possible to have a ratio R of value equal to 0.8. Likewise, the curves referenced 52, 54, 56 and 58 correspond to the pairs of values (ER; WNw) making it possible to have a ratio R of value equal to 0.2, 0.4, 0.6 and 1 respectively. to produce a semiconductor device 100 having a ratio R greater than 0.8, the values of ER and WNw can be chosen in the zone 60 on the right of the curve 50 and which corresponds to the pairs of values (ER WNw) leading to a ratio R greater than or equal to 0.8. This FIG. 7 shows that the more the structure of the semiconductor nanowires 104 is fine, that is to say the smaller the value of WNw (for example equal to 5 nm), the more the dielectric material used for producing the portions 108 can be chosen with a lower dielectric permittivity (for example HfO2 whose relative permittivity is equal to approximately 25 when WNW = 5 nm). Likewise, the larger the structure of the semiconductor nanowires 104, ie the larger the value of WNW (for example equal to 10 nm), the higher the dielectric material used for producing the portions 108. can be chosen with a higher dielectric permittivity (for example TiO2 whose relative permittivity is equal to about 80 when WNW = 10 nm). With such a ratio R close to 1 or between about 0.8 and 1, the electric potential obtained in the semiconductor nanowires 104 during operation of the semiconductor device 100 is relatively homogeneous, that is to say that the electrical potential at the upper and lower faces of the semiconductor nanowires 104 is almost equivalent to that at the side faces of the semiconductor nanowires 104 which are covered by the gate dielectric 110 and the gate 112 of the device semiconductor 100. It is possible that several semiconductor devices 100 made on the same layer or the same substrate form a single device FET type. In this case, the source and drain regions of these devices 100 are common, that is to say electrically connected to each other for example by unifying them such that they correspond to only one source region and to one another. only one drain region, and the grids of these devices 100 are also common such that the device obtained has only one grid. We will now describe, in connection with FIGS. 2 to 6B, the steps of a method for producing the semiconductor devices 100 previously described. A stack of several layers is first made to form the semiconductor nanowires 104 (see Figure 2 corresponding to a profile sectional view of this stack). This stack of layers rests on a support corresponding here to the dielectric layer 102. Several semiconductor layers 114 for the realization of the semiconductor nanowires 104 are arranged on the dielectric layer 102. The material of the semiconductor layers 114 corresponds to to that of the semiconductor nanowires 104 intended to be made, that is to say for example silicon and / or germanium and / or any type III-V semiconductor. The number of these stacked semiconductor layers 114 corresponds to the number of superimposed semiconductor nanowires 104 that each semiconductor device 100 is intended to have (three in the example described here). In addition, the thickness of these semiconductor layers 114 (dimension along the Z axis) is here equal to the height, or the desired thickness, HNW of the semiconductor nanowires 104. of each semiconductor device 100, the superimposed semiconductor nanowires 104 are also spaced apart from each other, the semiconductor layers 114 are spaced apart from one another by sacrificial layers 116 which are based on at least one material which can be selectively etched with respect to the semiconductor material of the layers 114, the thickness of the sacrificial layers 116 being here equal to the height, or thickness, HHK desired portions of dielectric material 108. The stack of layers therefore corresponds here to an alternating stack of N layers of semiconductor 114 and (N-1) sacrificial layers 116, with N integer greater than or equal to 2. In the example described here, the semiconductor layers 114 are based on e silicon, and the sacrificial layers 116 are based on SiGe. The concentration of germanium in the SiGe alloy of the sacrificial layers 116 is, for example, equal to approximately 20%, 30% or even 45%. The higher the germanium concentration in the SiGe of the sacrificial layers 116, the greater the etch selectivity towards the semiconductor layers 114 will be when removing the SiGe to form the semiconductor nanowires 104. Stacking of the semiconductor layers 114 and the sacrificial layers 116 can be obtained via the implementation of epitaxial steps.
    [0017] An etching step, here an anisotropic dry etching, of the stack of layers 114, 116 is then implemented so that the remaining portions of the semiconductor layers form the semiconductor nanowires 104. The sacrificial layers 116 and the layers semiconductor 114 are etched in the same pattern. Thus, the nanowires 104 superposed one above the other and intended to be part of the same semiconductor device 100 are spaced apart from each other by remaining portions 118 of the sacrificial layers 116, each of these remaining portions 118 being in contact with the two semiconductor nanowires 104 between which the remaining portion 118 is disposed. This etching step thus forms in the stack of empty spaces 120 intended to delimit and separate the different semiconductor devices 100 from each other. FIGS. 3A and 3B respectively represent a profile sectional view and a front sectional view (along the axis BB 'shown in FIG. 3A) of the stack after the implementation of this etching step. This etching step may be preceded by a lithography step in which the pattern to be etched in the stack of layers 114, 116 is defined by a mask formed on this stack of layers 114, 116. Advantageously and when the devices semiconductors 100 are intended to be made with a high density on the support, this mask can be achieved via the implementation of a "spacer patterning" or "double patterning" method as previously described in the prior art part. As shown in FIGS. 4A and 4B, the portions of the remaining portions 118 of sacrificial material lying between the semiconductor nanowires 104 are removed via selective etching relative to the semiconductor of the nanowires 104, for example of the CF4 plasma type. / N2 / Ar. Only the sacrificial material of the remaining portions 118 located at the channels to be formed by the nanowires 104 is etched, so that remaining portions 122 of SiGe portions 118 maintain the nanowires 104 at the level of referenced source and drain regions 126 and 128. This etching step forms, between the superposed nanowires 104 on top of one another, free spaces 124 whose dimensions and shape correspond to those of the etched portions of sacrificial material. correspond to those of the dielectric structures intended to be produced between the semiconductor nanowires 104. The dielectric interface layers The electrodes 106 are then made, for example by deposition, around the semiconductor nanowires 104 (see FIGS. 5A and 5B). Part of the free spaces 124 is filled with a part of the dielectric structures intended to be interposed between the semiconductor nanowires 104, this part of the dielectric structures corresponding to the portions of the dielectric interface layers 106 arranged between the semiconductor nanowires. driver 104 superimposed. When these dielectric interface layers 106 are based on semiconductor oxide, for example based on SiO 2, these dielectric interface layers 106 can be made by oxidation (for example of the plasma type, forming a deposit) of the semiconductor surface of the semiconductor nanowires 104. A dielectric material with a high dielectric permittivity (relative permittivity greater than 3.9) is then deposited in the set of voids previously formed in the stack of layers, c that is to say in the free spaces 124 between the superimposed semiconductor nanowires 104 and in the void spaces 120 separating the semiconductor nanowires 104 from the different semiconductor devices 100. The deposited dielectric material is then etched in order to keep only the portions of dielectric material located between the superimposed semiconductor nanowires 104 of the same semiconductor device 100, thus forming the portions of dielectric material 108 (see FIGS. 6A and 6B). At their ends, the portions of dielectric material 108 are juxtaposed with the source and drain regions 126, 128, and are in contact with source and drain extension areas between the channel regions formed by the semiconductor nanowires 104 and source and drain regions 126, 128. The portions of dielectric material 108 may also be in contact with the source and drain regions 126, 128.
    [0018] The gate dielectric 110 and the gate 112 are then made by depositing on the whole of the previously obtained structure, and then by etching the parts of the gate dielectric 110 and gate 112 materials not covering the upper faces and the sidewalls. side of the stacks of the semiconductor nanowires 104, dielectric interface layers 106 and portions of dielectric material 108. The semiconductor devices 100 obtained correspond to those shown in FIG. 1. According to an alternative embodiment, when the semiconductor nanowires 104 are not surrounded by the dielectric interface layers 106, the step previously described in connection with FIGS. 5A and 5B is not implemented, the dielectric material deposited and etched during the described step in connection with FIGS. 6A and 6B and intended to form the portions 108 then being in direct contact with the semiconductor nanowires The variant according to which the portions of dielectric material 108 are narrower than the nanowires 104 can be obtained via the implementation of a slight over-etching, for example of the humic type, of the dielectric portions 108; etching being performed before the deposition and etching of gate dielectric 110 and gate 112.25
    权利要求:
    Claims (13)
    [0001]
    REVENDICATIONS1. A semiconductor device (100) comprising at least: - two semiconductor nanowires (104) superimposed one above the other, spaced from one another and intended to form channel regions of the semiconductor device (100), - a dielectric structure (106, 108) completely filling a space (124) extending between the two semiconductor nanowires (104) and which is in contact with the two semiconductor nanowires conductor (104), - a gate dielectric (110) and a gate (112) covering at least a first of the two semiconductor nanowires (104), side flanks of the two semiconductor nanowires (104) and lateral flanks of the dielectric structure (106, 108), and wherein the dielectric structure (106, 108) has at least one dielectric material portion (108) of relative permittivity greater than 3.9.
    [0002]
    2. semiconductor device (100) according to claim 1, wherein the portion of dielectric material (108) comprises at least one dielectric material of relative permittivity greater than or equal to 20.
    [0003]
    3. semiconductor device (100) according to one of the preceding claims, wherein the semiconductor nanowires (104) are parallel to each other.
    [0004]
    The semiconductor device (100) according to claim 3, wherein each semiconductor nanowire (104) comprises, in a plane perpendicular to a direction in which the semiconductor nanowires (104) extend, a section of rectangular shape.
    [0005]
    The semiconductor device (100) according to one of the preceding claims, wherein each semiconductor nanowire (104) is surrounded by a dielectric interface layer (106), the dielectric structure (106, 108) further comprising portions of the dielectric interface layers (106) disposed between the semiconductor nanowires (104) and in contact with the dielectric material portion (108).
    [0006]
    6. semiconductor device (100) according to one of the preceding claims, further comprising, when the semiconductor device (100) comprises more than two semiconductor nanowires (104) superimposed one above the other , a plurality of dielectric structures (106, 108) such that two of the adjacent semiconductor nanowires (104) are spaced from each other by one of the dielectric structures (106, 108) extending between said two nanowires adjacent semiconductor nanoparticles (104), wherein the gate dielectric (110) and gate (112) further cover side flanks of each of the adjacent semiconductor nanowires (104). semiconductor nanowires (104) and side flanks of each of the dielectric structures (106, 108).
    [0007]
    The semiconductor device (100) according to one of the preceding claims, further comprising source and drain regions (126, 128) between which the semiconductor nanowires (104) extend, the dielectric structure (106, 108) being in contact with the source and drain regions (126, 128) and / or juxtaposed with the source and drain regions (126, 128).
    [0008]
    8. A method of producing a semiconductor device (100), comprising at least the steps of: - producing at least two semiconductor nanowires (104) superimposed one above the other, spaced from each other and intended to form channel regions of the semiconductor device (100), - providing at least one dielectric structure (106, 108) completely filling a space (124) extending between the two semiconductor nanowires (104) and which is in contact with the two semiconductor nanowires (104), - producing a gate dielectric (110) and a gate (112) covering at least a first two semiconductor nanowires (104), side flanks of the two semiconductor nanowires (104) and side flanks of the dielectric structure (106, 108), and wherein the dielectric structure (106, 108) comprises minus a portion of dielectric material (108) of relative permittivity greater than 3.9.
    [0009]
    9. A method of producing a semiconductor device (100) according to claim 8, wherein the realization of the two semiconductor nanowires (104) comprises at least the implementation of the steps of: - etching a stacking at least two semiconductor layers (114) between which at least one sacrificial layer (116) is disposed, such that remaining portions of the two semiconductor layers (114) correspond to the semiconductor nanowires (104) a remaining portion (118) of the sacrificial layer (116) being disposed between the semiconductor nanowires (104); - removing the remaining portion (118) of the sacrificial layer (116) disposed between the semiconductor nanowires (116); conductor (104) forming the gap (124) extending between the two semiconductor nanowires (104).
    [0010]
    The method of making a semiconductor device (100) according to claim 9, wherein the two semiconductor layers (114) comprise silicon, and the sacrificial layer (116) comprises SiGe.
    [0011]
    11. A method of producing a semiconductor device (100) according to one of claims 8 to 10, wherein the step of producing the dielectric structure (106, 108) comprises at least one deposit of the portion of dielectric material (108) between the semiconductor nanowires (104).
    [0012]
    12. A method of producing a semiconductor device (100) according to claim 11, wherein the step of producing the dielectric structure (106, 108) further comprising, between the step of producing the two nanowires of semiconductor (104) and the step of depositing the portion of dielectric material (108), a step of producing a dielectric interface layer (106) around each semiconductor nanowire (104), the portion of dielectric material (108) being subsequently deposited against portions of the dielectric interface layers (106) disposed between the semiconductor nanowires (104).
    [0013]
    13. A method of producing a semiconductor device (100) according to one of claims 8 to 12, further comprising the production of source and drain regions (126, 128) between which the nanowires of semiconductor (104), the dielectric structure (106, 108) being made in contact with the source and drain regions (126, 128) and / or juxtaposed with the source and drain regions (126, 128).
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1450079A|FR3016237B1|2014-01-07|2014-01-07|SEMICONDUCTOR NANOWELL DEVICE PARTIALLY SURROUNDED BY A GRID|FR1450079A| FR3016237B1|2014-01-07|2014-01-07|SEMICONDUCTOR NANOWELL DEVICE PARTIALLY SURROUNDED BY A GRID|
    US14/581,029| US9728405B2|2014-01-07|2014-12-23|Nanowire semiconductor device partially surrounded by a gate|
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